Questions on combinational logic

Question 1

Explain why a digital signal is far less affected by noise on a long cable than an analogue signal carrying the same information.

Accepted Answer

An analogue signal carries its information in its exact shape, so any noise added on the way becomes part of the signal and cannot afterwards be told apart from it (1). A digital signal has only two meaningful levels, and the receiver asks only whether each pulse is above or below a threshold, so noise smaller than half a logic level leaves the decision unchanged (1).

Question 2

State the difference between regenerating a digital signal and amplifying an analogue one.

Accepted Answer

Each amplifier also amplifies the accumulated noise, so signal quality progressively deteriorates (1). A regenerator detects each bit and produces a new standardised pulse, removing amplitude noise accumulated before that point (1).

Question 3

Write out the truth table of an EOR gate, and state in one sentence what it does.

Accepted Answer

A = 0 B = 0 → 0
A = 0 B = 1 → 1
A = 1 B = 0 → 1
A = 1 B = 1 → 0
The output is 1 when the inputs differ (2). The EOR and OR tables differ only in the last row, A = 1, B = 1, where OR gives 1 and EOR gives 0.

Question 4

Write out the truth table of a NAND gate, and state its relationship to the AND gate.

Accepted Answer

A = 0 B = 0 → 1
A = 0 B = 1 → 1
A = 1 B = 0 → 1
A = 1 B = 1 → 0
NAND is AND with the output inverted, drawn with a small circle on the output (2). Every other gate can be built from NAND gates alone. Check the first row: NAND gives 1 when both inputs are 0.

Question 5

Describe the behaviour of a D-type flip-flop.

Accepted Answer

On each rising edge of the clock it copies whatever is on the data input D to its output Q (1), and it then holds Q frozen until the next clock edge, ignoring D completely in between (1). That is what makes it a one-bit memory; registers and computer memory are rows of them.

Question 6

State the relationship between the input and output frequencies of a chain of n toggling flip-flop stages.

Accepted Answer

f_out = f_in/2ⁿ (1). Every stage halves the frequency once. The number of states is also 2ⁿ, but it is a count of states rather than a division of frequency.

Question 7

A logic circuit has output Q = (A OR B) AND NOT C. Construct its full truth table, with the inputs in binary counting order, and state how many input combinations give Q = 1.

Accepted Answer

Three inputs give 2³ = 8 rows, taken in binary order (1):
A = 0 B = 0 C = 0 → 0
A = 0 B = 0 C = 1 → 0
A = 0 B = 1 C = 0 → 1
A = 0 B = 1 C = 1 → 0
A = 1 B = 0 C = 0 → 1
A = 1 B = 0 C = 1 → 0
A = 1 B = 1 C = 0 → 1
A = 1 B = 1 C = 1 → 0
Q = 1 for 3 of the eight combinations (2). Note that C = 1 forces Q = 0 whatever A and B do, because the NOT C term feeds an AND.

Question 8

A chain of 10 toggling flip-flop stages is clocked at 1.024 MHz. Calculate the frequency at the output of the final stage.

Accepted Answer

Each stage halves the frequency, so ten stages divide by 2¹⁰ = 1024 (1). f_out = 1.024 × 10⁶/1024 (1) = 1000 Hz (1). Dividing by 10 rather than by 2¹⁰ gives an answer about a hundred times too large.

Question 9

A timing circuit is clocked at 2.048 MHz and must produce an output at 250 Hz. Calculate the number of toggling flip-flop stages required.

Accepted Answer

Division needed = 2.048 × 10⁶/250 = 8192 (1). 8192 = 2¹³ (1), so 13 stages are needed (1). The number of stages is a whole number: each stage divides by two, so the overall division is an exact power of two and a non-integer result indicates an arithmetic error.

Question 10

A binary counter is built from 6 toggling flip-flop stages and clocked at 4096 Hz. State the number of distinct states it passes through, the range of counts it displays, and the frequency at its final output.

Accepted Answer

Number of states = 2⁶ = 64 (1), displayed as the counts 0 to 63 (1). Final output frequency = 4096/2⁶ = 64 Hz (1). The counts run from 0 to 63, not 1 to 64.

Question 11

A half-adder adds two single binary digits A and B. Name the gate that produces each of its two outputs, and give the sum and carry for every combination of the inputs.

Accepted Answer

The sum comes from an EOR gate, since the sum is 1 exactly when the inputs differ, and the carry from an AND gate, since the carry is 1 exactly when both inputs are 1; both share the same pair of inputs (2). A = 0, B = 0 → sum 0, carry 0 A = 0, B = 1 → sum 1, carry 0 A = 1, B = 0 → sum 1, carry 0 A = 1, B = 1 → sum 0, carry 1 Every row agrees with ordinary arithmetic, the carry read before the sum (1). An OR gate does not give the sum: it fails on the last row, where 1 + 1 must give sum 0 and carry 1.

Question 12

An alarm sounds (Q = 1) when a door is open (D = 1) and the system is armed (R = 1) and the override key is not inserted (K = 0). Write the Boolean expression, name the gates required, and give Q for the three cases D = 1, R = 1, K = 0; D = 1, R = 1, K = 1; and D = 0, R = 1, K = 0.

Accepted Answer

Q = D AND R AND NOT K (1), needing one NOT gate feeding a three-input AND, or two two-input ANDs in series (1).
D = 1 R = 1 K = 0 → 1
D = 1 R = 1 K = 1 → 0
D = 0 R = 1 K = 0 → 0
Only the first case sounds the alarm (1). Translate the sentence one connective at a time: 'and the key is not inserted' is an AND with a NOT, and dropping the NOT would let an inserted key sound the alarm.

Question 13

A logic system uses 0 V for logic 0 and 5.0 V for logic 1, with a decision threshold at 2.5 V. A pulse sent at 4.6 V arrives with 0.9 V of noise subtracted from it. State the voltage at the receiver, and state whether the pulse is read correctly.

Accepted Answer

The pulse arrives at 4.6 − 0.9 = 3.7 V (1). That is still above the 2.5 V threshold, so it is read as logic 1 and the pulse is correct; the margin available was 2.1 V (1).

Question 14

An astable's output is high for 4.0 ms and then low for 1.0 ms, repeating. State the pulse width, calculate the frequency, and give the mark-to-space ratio and the duty cycle.

Accepted Answer

The pulse width is the high time on its own, 4.0 ms (1). The period is 4.0 + 1.0 = 5.0 ms, so f = 1/(5.0 × 10⁻³) = 200 Hz (1). Mark-to-space ratio = 4.0/1.0 = 4.0, written 4:1 (1). Duty cycle = 4.0/5.0 = 80% (1). Keep the two ratios apart: mark-to-space compares the high time with the low time, duty cycle compares the high time with the whole period.

Question 15

A 5-stage Johnson counter and a 5-stage binary ripple counter are each clocked at 2.0 kHz. State the number of distinct states each passes through, calculate the time each takes to complete one full cycle, and give one reason a designer chooses the Johnson counter where the outputs are used as timing signals.

Accepted Answer

A Johnson counter of n stages has 2n states, so five stages give 10 states, while the ripple chain has 2⁵ = 32 (1). One state lasts one clock pulse, and the clock period is 1/2000 = 0.50 ms, so the Johnson counter completes a cycle in 10 × 0.50 = 5.0 ms (1) and the ripple counter in 32 × 0.50 = 16 ms (1), which is also the period of its final stage, running at 2000/2⁵ = 62.5 Hz. In the Johnson counter only one output changes at each step, so its outputs never pass through a code that does not belong to the count, while a ripple chain's stages toggle one after another and do show such codes on the way (1). A Johnson counter of five stages has 10 states, not 2⁵ = 32: most of the available combinations are given up, and clean ordering is what is bought with them.

Question 16

A pump must run (P = 1) when the tank level is low (L = 1), unless the manual stop is pressed (S = 1). It must also run whenever the test button is pressed (T = 1), whatever the other two inputs are doing. Construct the full truth table, write the Boolean expression, name the gates needed, and state how many of the eight input combinations run the pump.

Accepted Answer

Three inputs, so eight rows in binary counting order (2):
L = 0 S = 0 T = 0 → 0
L = 0 S = 0 T = 1 → 1
L = 0 S = 1 T = 0 → 0
L = 0 S = 1 T = 1 → 1
L = 1 S = 0 T = 0 → 1
L = 1 S = 0 T = 1 → 1
L = 1 S = 1 T = 0 → 0
L = 1 S = 1 T = 1 → 1
The pump runs in 5 of the eight combinations (1). Reading the specification straight off gives P = (L AND NOT S) OR T (2). The circuit needs one NOT gate on S, one AND combining L with NOT S, and one OR bringing in T (2). Check the two authorities in the table: with T = 0 the stop button always wins, and with T = 1 the output is 1 in every row. Feeding T into the AND would let the stop button defeat the test, and dropping the NOT would make pressing stop run the pump.

Question 17

A quartz watch runs from a crystal at 4 194 304 Hz. Calculate the number of toggling stages needed to produce a once-per-second tick, and calculate the frequency available at the output of the twelfth stage.

Accepted Answer

4 194 304 = 2²² (1), so 22 stages take the frequency down to exactly 1 Hz (1). After twelve stages the frequency is 4 194 304/2¹² = 4 194 304/4096 (1) = 1024 Hz (1). Crystal frequencies are chosen as powers of two for precisely this reason. Dividing by 12 rather than by 2¹² uses the number of stages in place of the division they perform.

Question 18

A full adder adds two bits A and B together with a carry brought in from the column to its right. It is built from two half-adders and an OR gate. Explain how the two half-adders are connected, and give the sum and carry outputs when A = 1, B = 1 and the incoming carry is 1.

Accepted Answer

The first half-adder adds A and B, producing an intermediate sum and an intermediate carry (1). The intermediate sum and the incoming carry go into the second half-adder, whose sum is the final sum bit; the two intermediate carries are combined by the OR gate to give the final carry out (1). For A = 1, B = 1, carry in 1: the first half-adder gives sum 0 and carry 1; the second adds that 0 to the incoming 1, giving sum 1 and carry 0; the OR gate passes the first carry, so carry out = 1 (1). Read together the answer is binary 11, the number three, which is 1 + 1 + 1 (1). The carry cannot enter the first half-adder, which has only two inputs.

Question 19

A digital link uses 0 V and 5.0 V logic levels with the threshold midway. Noise accumulates at 0.35 V per kilometre of cable, and the receiver is reliable while the accumulated noise stays below 1.2 V. Calculate the greatest whole number of kilometres between regenerators, and the number of regenerators needed on a 30 km route. Explain why an analogue link over the same route cannot be rescued the same way.

Accepted Answer

Distance before the noise reaches 1.2 V = 1.2/0.35 = 3.43 km, so regenerators go every 3 km (1). A 30 km route is then 30/3 = 10 sections, which needs 9 regenerators along the way, the receiver ending the last section (1). Each regenerator reads every pulse as 0 or 1 while the noise is still well inside the margin and issues a clean new pulse, so the noise never accumulates beyond one section's worth (1). On an analogue link the noise is indistinguishable from the signal, so an amplifier boosts both and the degradation is permanent and cumulative (1). The spacing must be rounded down: at 4 km the noise passes the margin before the next regenerator is reached.

Question 20

A chain of four toggling flip-flop stages counts clock pulses. Explain how the chain is made to count modulo 10, and state the range of counts it then displays.

Accepted Answer

The outputs that are high at the count of ten, 1010, are wired into a NAND gate (1); the gate's output feeds the reset input of every stage, so the instant that count appears the whole chain is cleared and the count never persists there (1). The counter therefore displays 0000 up to 1001, the counts 0 to 9, before starting again from zero: a decade counter (1).

Question 21

An astable switches a lamp through a MOSFET. Its output is high for 2.0 ms and low for 6.0 ms, and the lamp may be modelled as a constant resistance of 8.0 Ω across a 12 V supply. Calculate the frequency and the duty cycle of the astable, and calculate the average power delivered to the lamp. The resistance in the charging path that sets the low time is then halved: calculate the new frequency and the new average power.

Accepted Answer

The period is 2.0 + 6.0 = 8.0 ms, so f = 1/(8.0 × 10⁻³) = 125 Hz (1). Duty cycle = 2.0/8.0 = 25% (1). With the channel fully open the lamp would take P = V²/R = 12²/8.0 = 18 W (1). The MOSFET is fully on for that fraction of each period and fully off for the rest, so the average power is 0.25 × 18 = 4.5 W (1). Halving that resistance halves the low time to 3.0 ms, so the period becomes 5.0 ms, f = 200 Hz and the duty cycle rises to 2.0/5.0 = 40%, giving an average power of 7.2 W (1).